We are hiring! Are you passionate about physical chip design and working through complex challenges? We need you. In this role, you will take full ownership of the implementation process at the top level of an enormous design—from RTL to GDSII—utilizing some of the industry's most advanced technology nodes. ! As a Physical Implementation Engineer, you will take ownership of the physical implementation process, from physical chip design to chip production and post-silicon validation. You will work with cutting-edge technology, collaborating closely with external IP providers, EDA vendors, and silicon/package vendors to deliver high-performance SoCs or SiPs for mass production.

What do we offer? Flexible work schedules, competitive pay, a highly collaborative learning environment, and opportunities for career growth. Come and join us in the beautiful city of Barcelona! Candies, coffee, and free Spanish lessons included! (Visa sponsorship available if required.).

Key Responsibilities

• Top Level/Full Chip implementation engineer.
• Experience of top level design planning, partitioning, and clock tree planning with many blocks including multiply instantiated modules ( MiM’s)
• Experience with mixed top down design/bottom up design planning flows.
• Understanding and ability to implement various clock tree strategies ( basic, Htree, Mesh, Multisource CTS)
• Significant knowledge of and ability to contribute to top level STA and Physical verification as required.
In conjunction with the STA
• engineer able to coordinate and drive block level timing and verification fixes required at block levels.

• Master’s or PhD degree in Computer Science, Microelectronics, or Physics.
• Proven experience with multiple ( > 2) tapeouts of high-performance SoCs or SiPs.
• Expert user of Synopsys tool suite ( Fusion Compiler &/or ICC2 + Primetime ) tools.
• Experience with Physical Verification tools ( ICV/Calibre)
• Advanced scripting skills in Tcl/Perl/Python for tool control and manipulation nand data extraction.
• Experienced in using revision control systems, preferably GIT.

Additional Able to guide and mentor

• engineers.
Preferable acted as Physical Design
• for at least 2 hierarchical designs in advanced nodes