Interviewer was more focused on trivial things like syntax of the program rather than the actual logic and the solution. Insisted on fixing syntax issues. Questions were themselves simple. The interview process itself seemed like they were not interested in hiring (interview during the mass layoffs time)

Had 4 rounds ( 2 technical, 1 Behavioral, 1 Technical), Being strong in the System Verilog fundamentals should help you out. Coding questons are tricky a bit which tests knowledge on multiple concepts of SV and UVM.