Strong hands-on experience in RTL coding using VHDL/Verilog HDL, Simulations, working knowledge in Digital circuit design, high speed interface circuits, system integration testing and Lab testing. Responsible for complete product development and deliverables, right from Architecture and spec finalization to FPGA proto-type targeted on Xilinx. Kintex 7, including Architecture, Functional Specifications Documentation,RTL Design documentation, RTL, STA, Simulations, Synthesis, Good Understanding of ASIC Design flow and Customer Support.

Run through the basic hardware level questions on signal integrity and timing violation checks. basic questions on the previous projects Dynamic memory allocation program Next round was Managerial level where he tried to check the problem solving skills