El proceso duró 3 días. Acudí a una entrevista en Intel Corporation (Hillsboro, OR) en abr 2011
Entrevista
Received an email from the Physical Design team of Intel Corporation few days back. Included details of what to be expected and what they will offer. More of layout and design on Analog/Digital/RF/IO circuits , academic background they were looking for. Didn't tell me of the duration of interview and started with HR questions followed by technical questions mostly on CMOS Digital circuits.
Preguntas de entrevista [2]
Pregunta 1
CMOS Inverter , how to reduce the drive strength of Minimum size inverter
Acudí a una entrevista en Intel Corporation (Petah Tikva)
Entrevista
very nice people. given 2 question one on system of the group and one for coding in binary search and recursion. we started by little talking and then a little bit on one of the project and then 2 questions
Preguntas de entrevista [1]
Pregunta 1
1. given graph and car with light sensor and we want to find the right spot of the dot on the graph. it was binary search classical
Envié una solicitud electrónica. Acudí a una entrevista en Intel Corporation (Bengaluru) en may 2026
Entrevista
Deep whiteboard interview , was asked to draw graphs for non ideal characteristics for cmos design and pvt corners. Questions related to project and physical design concepts. Focused on semiconductor physics and technical depth in each answer.
Preguntas de entrevista [1]
Pregunta 1
was asked to draw graphs for non ideal characteristics for cmos design and pvt corners.Questions related to project and physical design concepts. Focused on semiconductor physics and technical depth in each answer.
Acudí a una entrevista en Intel Corporation (Austin, TX)
Entrevista
This was the second round lasted about an hour or so. The first round was mostly about my work as I had 3 year experience and I had to walk them through the projects I did etc..,.
Preguntas de entrevista [1]
Pregunta 1
If the combination logic between 2 FF's is cut like an interface, how do you set_input_delay and set_output_delay for left and right partitions. The clock is the same for both.
