since everyone is just advertising, let me actually try answering the question for people who want to know. setup time violation is when the data that is expected does not make it to the flip flop or register in time (usually by the next clocking edge). in general, the way to calculate it is by determining how long it will take for a datapath to go (at the rising edge of one flop) from the exit of the launching flop, through the combinational circuitry, and then land at the destination flop. best to measure worst case scenario for this. at the same time, measure how long it takes for a clock edge to travel from one flop to the next + the time of one cycle. best to measure most optimal time for this. the subtraction of worst case data path timing from best case clock timing will tell you how much time you have. positive is is a violation (you need more time than the clock period gives) , negative is good (your clock period is bigger than the time needed). hold violations are something special but important. at the micro level, if two flops are connected by the same clock, it does not mean that both will get the rising edge at the same time. there will be some clock skew that exists due to RC of the wire, or gates on the clock path. what you want to make sure of is that when the launch flop gets a rising edge, the data that is launched does NOT go through the combinational logic and make it to the destination flop BEFORE the destination flop sees the same rising edge. there was data that was supposed to be latched on that rising edge. failing this would mean that the data that should have been latched will be lost and the new data that was launched will in essence bypass this destination flop (as it will have continued to flow on the same clock edge).