Interview will be very minimal, mostly Verilog+SystemVerilog+simulation+debug skills. Methodology will be an added advantage. Also having a protocol knowledge will be an advantage. Most importantly, communication skills.

Got a phone call from a hiring manager who asked me to come interview for this position. I told him that I am only a recent graduate, and might not be a fit for this senior role upon reading the position description. He still insisted for me to come in. I came in after 2 business days, and we didn't even talk for more than 20 minutes before he admitted that this position was a bit too "senior" for me (as I have alluded to him in our first conversation), and he told me at the spot that he cannot move me forward. Even though it was a waste of my time, but at least he was polite and courteous during the duration of the full interview. I would suggest to their hiring manager to get better assessment skills for screening , since it was obvious that the specific hiring manager I talked to had difficulty weighing my skills over the phone, and believed I was a fit for this senior role.