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      Búsquedas relacionadas: Opiniones sobre Marvell Technology | Ofertas de empleos en Marvell Technology | Sueldos en Marvell Technology | Beneficios en Marvell Technology
      Entrevistas de Marvell TechnologyEntrevistas para el puesto de Logic Design Engineer en Marvell TechnologyEntrevista de Marvell Technology


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      Entrevista de Logic Design Engineer

      24 sept 2015
      Candidato de entrevista anónimo
      Sin oferta
      Experiencia positiva
      Entrevista normal

      Solicitud

      Acudí a una entrevista en Marvell Technology

      Entrevista

      I got a phone interview the other day directly from a current employee from their CPU group. He asked me about the basic concepts in computer architecture and it was not very hard. Also, he asked a lot about work experiences showed on my resume.

      Preguntas de entrevista [1]

      Pregunta 1

      basic cache related questions
      Responder pregunta

      Otras opiniones sobre las entrevistas para el puesto de Logic Design Engineer en Marvell Technology

      Entrevista de Logic Design Engineer

      10 mar 2016
      Empleado anónimo
      San Jose, CA
      Oferta aceptada
      Experiencia positiva
      Entrevista normal

      Solicitud

      Solicité el puesto a través de la escuela superior o la universidad. El proceso duró 3 semanas. Acudí a una entrevista en Marvell Technology (San Jose, CA) en feb 2016

      Entrevista

      My resume was referred to CPU group through an alumni from umich. Around 1 months after I submitted my resume, I got an email from the hiring manager. He asked me what was the good day for the phone interview. The phone interview took half an hour. One logic engineer asked me some basic questions about 5 stage in order pipeline and something about my resume. After 2 weeks came the invitation for onsite interviewIt. It took half day for meeting 5 people. Each interviewer spent ~ 30 minutes and asked ~ 5 questions. Each interviewer asked questions in the different areas.

      Preguntas de entrevista [2]

      Pregunta 1

      Do we need PC to index second level table of branch predictor (i.e. pattern history table)? Why? What if bits of PC more than bits to index to pattern history table?
      1 respuesta

      Pregunta 2

      How can we use PRF to implement CMOV instruction?
      1 respuesta
      2

      Entrevista de Logic Design Engineer

      4 sept 2014
      Empleado anónimo
      Oferta aceptada
      Experiencia positiva
      Entrevista normal

      Solicitud

      Envié una solicitud electrónica. Acudí a una entrevista en Marvell Technology

      Entrevista

      Heard about job openings through a friend that was contacted by a recruiter. E-mailed my resume to the recruiter and was invited for short on-site interviews with two different teams: CPU logic design and SoC verification. I was only brought on-site for the first step because I was living in Santa Clara at the time. After the two interviews, I was later invited back for a full day of on-site interviews with the CPU team. I interviewed with 5 different members of the CPU team. I thought I did really well with the interviews but it still took Marvell weeks to get back to me with an official offer.

      Preguntas de entrevista [1]

      Pregunta 1

      Questions were related to logic design and computer architecture. With a good understanding of pipeline design and out-of-order execution principles the questions were not too hard. The only question that I couldn't really solve was about the design of a scalable, fair arbiter. Expect questions about out-of-order execution algorithms, state machine design, and logic optimization.
      Responder pregunta
      1

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