How would you debug a failing simulation where coverage is not met?
Anónimo
I start by analyzing the coverage report to identify missing bins. Then I review the sequence generation logic and constraints to ensure edge cases are being stimulated. I inspect logs and waveforms to trace transaction flow and verify monitor-scoreboard connectivity. If needed, I inject directed sequences and refine constraints iteratively. I also validate that assertions are firing correctly and that the DUT is responding as expected.