I have gone through 2 rounds. 1. Technical interview Here mostly I got questions from my projects , sv and uvm related questions 2. Managerial round ( same as technical interview). The manager mostly asked the questions like , how we actually do the verification. Steps to do for verification process. Process of debugging. He gave me one question and ask me how will I debug that.

There was a written test and followed by two round of interviews for candidates who passed the written test. They focused more on Verilog code and asked questions about the projects.