I interviewed for the New College grad role. There was one screening round with the hiring manager (more of a discussion on projects done) and there were 6 rounds of interviews for the panel round.
Preguntas de entrevista [1]
Pregunta 1
Screening: Setup and Hold time violations Synthesis constraints (ideal path, false path) Open page and closed page policy DDR project in-depth Panel round: Round 1 Asynchronous FIFO: How to design and problems faced? Synchronous FIFO verilog code Round 2 What is a glitch? When can it occur? Explain with waveforms. How to resolve the problem of glitches? How to design glitch-free circuits Static and dynamic power, Ways to reduce both Given a list in Python Sort it without using sort() Setup and hold time constraints Round 3 Resume projects and experience Open page vs closed page policy What is pipelining Adding pipeline registers to the timing path: It’s impact on performance and area Round 4 Verilog code for a given problem: given x config(7), y config(6) Convert into corresponding x and y coordinates and trace the path (Can be done using fsm for tracing both x and y coordinates) Round 5 Verilog coding (Question related to rotating bits for a given number) Most challenging problem faced Round 6 Verilog arbiter code (3 requests), can store outstanding requests in fifo
It was good everyone were easy to talk to and helpful when stuck. Position experience. Questions were medium difficulty. It was related to asic design. Had an interview screening then panel interview
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Entrevista
Contacted by HR and had a brief phone screen to talk about past coursework and interest. 1st round technical interview on timing constraints, bus protocols, and verilog coding. Also digged into projects on resume.