Envié una solicitud electrónica. Acudí a una entrevista en Apple (Sunnyvale, CA) en oct 2025
Entrevista
1 Screening Round and once you get selected, they schedule 6 Panel Rounds back to back with different people (Clock Tree Synthesis (CTS), Static Timing Ananlysis (STA), Floorplan, PNR flow, Low Power design)
Preguntas de entrevista [1]
Pregunta 1
STA, CTS, Floor planning, Logic Circuits, PNR
1. What is OCV and derate factors
2. Calculation of setup and hold slack (Given values, Thold, Tsetup, Tlogic, derate factors)
3. How to reduce setup violations and hold violations?
4. Difference between H-tree and Mesh?
5. Techniques to reduce clock power?
6. Low power design techniques
7. What is Multi Bit FF?
8. Draw basic logic gates (And) using NOR (NAND) gates?
9. Crosstalk glitches?
10. Placement of macros questions
11. How to calculate channel spacing between macros/
12. SRAM design questions
13. Physical only cells- Tap cells, Tie cells use and where do we place them
14. How Delay of a net/cell changes with VDD/
15. Capacitance and Resistance of wire effects on delay and how to reduce it?
16. How to reduce static, Dynamic, short -circuit power?
17. Where to use LVT, HVT cells?
18. Difference between local skew and global skew?
19. Verilog Coding question- Synchronous and Asynchronous DFF
20. What is the use of End cap cells and Decap cells?
Received a technical screening call from a recruiter and later an interview call. Interviewer was friendly and supportive. He pulled up the resume and asked general questions about relevant experience and projects.
Preguntas de entrevista [1]
Pregunta 1
What was the major challenge you faced while working on this project?