Solicité el puesto a través de una agencia de empleo. Acudí a una entrevista en Analog Devices en feb 2025
Entrevista
I applied in the analog website, they made me a personal interview with the hr manager and then after 3 days a senior engineer made me the technical interview for the position of Digital Design intern
Preguntas de entrevista [1]
Pregunta 1
Design a D flipflop, Design a nand Gate with transistors, Explain the real output of the nand Gate, Explain the capacitance of the NAND gate and how It affects to trise and tfall Translate It in a MOSFET and get the capacitance,
design a layout of a nand Gate, he tried to Explain me somethimg if i didn't know how to do It and see if could learn from It and apply It in another cases
Solicité el puesto a través de la escuela superior o la universidad. Acudí a una entrevista en Analog Devices (Nūzvīd) en dic 2025
Entrevista
its two round written and interview happen on our campus at iiit Nuzvid. the questions include from mainly digital electronics and static timing analysis, signals and system, verilog programming language
Preguntas de entrevista [1]
Pregunta 1
asynchronus fifo and synchronous fifo and clock domain crossing
Acudí a una entrevista en Analog Devices (Bengaluru)
Entrevista
First we had an Online Test. Online Test has two sections in which first section is technical as I applied for digital design Engineer role. Time is 60 minutes we had 17-20 questions in which some of the questions are bit tricky. And second section has aptitude questions. Now shortlisting is done just before the interview only there is 3-4 hours gap so be prepared. My interview went for one and half hour in which two panels took my interview. It was a great experience.
Preguntas de entrevista [1]
Pregunta 1
1. Introduce Yourself 2. If you want to build a microcontroller from scratch what are the steps you will carry out? 3. Gave one question from FIFO depth calculation 4. Do you know anything about DFT? 5. Asked about projects that are mentioned in the resume. 6.What is Asynchronous FIFO? verilog code 7. Tell the logic for Asynchronous FIFO full and empty conditions? 8. Some HR questions
