Solicité el puesto a través de la recomendación de un empleado. El proceso duró 1 día. Acudí a una entrevista en AMD (Bengaluru) en ago 2014
Entrevista
There were three rounds. I cleared first two rounds. Third round was with manager, and it was a brainstorming round. They can ask you about anything. And the question is not, what you did. But, why you did that. Means if you have a chosen a path A, then what all paths you considered, pros and cons of each path, how did you finally arrive at path A. And how sure you are, that path A was the best. It was a good experience overall.
Preguntas de entrevista [1]
Pregunta 1
They asked about my project, basic and advance digital design, CMOS concepts, STA, C, Verilog
Envié una solicitud electrónica. El proceso duró 2 semanas. Acudí a una entrevista en AMD (Londres, Inglaterra) en ene 2026
Entrevista
1. HR call - slary expectation, relocation, general q/a
2. CV based interview with hiring manager (focusing on past relative work experinence)
3. 4 Tech interviews (problem solving, algorithms, job specific tech skills)
Preguntas de entrevista [1]
Pregunta 1
propose a design of the module based on provided specifications
It was smooth, i had three rounds with first being the screening. It was for internship so they mostly focused on intermediate level C++ programming for performance architecture role. It was a video interview via teams.
Telephone and video call,
Basics to projects
Resume based
Power sta front end
Back end
Synthesis
Vlsi
What are the challenge you will see in lower technology?
What are the inputs and outputs from the power analysis?
What are the checks after power planning is completed?
What are the power dissipation components? How to reduce them
Why float outputs are ignored but not float gates?
How do you calculate the core ring width?
What is IR drop? And how will you decrease this?
Preguntas de entrevista [1]
Pregunta 1
What are the challenge you will see in lower technology?
What are the inputs and outputs from the power analysis?
What are the checks after power planning is completed?
What are the power dissipation components? How to reduce them
Why float outputs are ignored but not float gates?
How do you calculate the core ring width?
What is IR drop? And how will you decrease this?
