Envié una solicitud electrónica. Acudí a una entrevista en AMD (Boxborough, MA)
Entrevista
Questions on FSM, difference between system verilog and verilog, coverage concepts. There were 5 interviews and it was very repetitive, I was asked to go over my resume and work experience 5 times, asking the same questions. For one of the interviews the interviewer was just reading my resume for almost 1 hour while I just sat on the other side of the screen waiting. For another of the interviews the interviewer was kind of mumbling and mentioning a lot of abbreviations. It was an ok experience but maybe they need to be more organized.
Preguntas de entrevista [1]
Pregunta 1
Design an FSM for an elevator, different kinds of coverage, describe some RTL bugs you found in your current role, describe UVM testbench, how are sequences and drivers connected
campus interview . 2 rounds, basic questions from STA , cmos, digital basics , verilog questions, verilog code for asynchronus d flipflop, blocking and non blocking statements, structure of 3 input OR gate, explain about static and dynamic power
1. HR Screen
2. Technical Round
The whole process was around 2 weeks.
You first get a call from the HR and then will answer questions.
If you are successful, you will book a time for a technical interview.
Preguntas de entrevista [1]
Pregunta 1
Tell me the difference between combinational and sequential logic
I was not well prepared, It was basic q and a related to my current role and some basic OSI questions, Also interviewer was great he gave me time to understand the question and helped me with the hints
Preguntas de entrevista [1]
Pregunta 1
A chip was given which performs (001)addition,(010) subtraction, (011)multiplication and division(100) on 8 bit value, it can store 20 operands at a time in a stack and 2 bits for error handling,
Arth overflow
Stack over
1.Questions was to find out end cases and possible errors and how can we handle it in verilog test benches?.
2. Also, How to write those test cases. ?