Pregunta de entrevista de AMD
1. Difference between SystemVerilog and Verilog. 2. Difference between nonblocking and blocking. 3. Difference between asynchronous and synchronous. 4. How can you observe and solve the problem if there is a timing violation (related to setup time and hold time)
Respuesta de la entrevista
Anónimo
29 oct 2021
Verilog can not written for test bench, system verilog can be, non blocking (<=) righthand side will get update after all lefthand values got change after clk pulse.