Simple and basic digital electronics questions were asked. Some Questions on verilog and HDL was also included. Basic system verilog and OOPS concepts are necessary. A good understanding of projects presented in the resume is very essential.
Having knowledge of fundamentals of VLSI will be helpful.
It was a smooth process, mostly technical problems, no tricky questions. Mostly asked about previous project on resume, with some coding questions at the end. Total 4hr with 4 different engineer/manager
The interview process consisted of two rounds. The first was a technical screen focusing on Verilog and RTL design. The second was a behavioral interview with the manager. nice processes overview
Solicité el puesto a través de la recomendación de un empleado. Acudí a una entrevista en Synopsys en mar 2025
Entrevista
hard. fifo's n all. and other designing questions. muxes, gates, cdc n all. designing n other implementation questions are their . tough questions were their. U get designing to the best.
Preguntas de entrevista [1]
Pregunta 1
ok. fifo..design n implementation.and other designing questions
