Solicité el puesto a través de la recomendación de un empleado. Acudí a una entrevista en Qualcomm (San Diego, CA) en may 2025
Entrevista
First i had a technical interview and then followed by HR round and then a panel round with 4 engineer it was a 1 on 1 interview.
basically the interview were schedule for 45 min with 1 Engineer. but mostly ended up for more than an 1hr.
Solicité el puesto a través de un captador. Acudí a una entrevista en Qualcomm en dic 2025
Entrevista
The interview process for an ASIC Design Verification (DV) Engineer typically includes resume screening, one or more technical phone or online interviews focusing on digital fundamentals, SystemVerilog, UVM, and debugging skills, followed by multiple in-depth technical and behavioral interview rounds assessing verification methodology, problem-solving ability, and teamwork.
Preguntas de entrevista [1]
Pregunta 1
They mainly asked me to explain how to build and debug a UVM-based verification environment, including the roles of sequences, drivers, monitors, scoreboards, and how I handled a real bug or coverage issue during a project.
